spo600:aarch64_register_and_instruction_quick_start
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spo600:aarch64_register_and_instruction_quick_start [2024/02/02 15:14] – [AArch64 Register and Instruction Quick Start] chris | spo600:aarch64_register_and_instruction_quick_start [2025/02/19 16:54] (current) – [General-Purpose Integer Registers] chris | ||
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===== AArch64 Register and Instruction Quick Start ===== | ===== AArch64 Register and Instruction Quick Start ===== | ||
- | This page contains very basic information on the AArch64 mode of the [[ARMv8]]/ARMv9 architecture: | + | This page contains very basic information on the AArch64 mode of the [[ARMv8|ARMv8/ARMv9]] architecture: |
===== | ===== | ||
- | ==== General-Purpose Registers | + | ==== General-Purpose |
The aarch64 registers are named: | The aarch64 registers are named: | ||
* r0 through r30 - to refer generally to the registers | * r0 through r30 - to refer generally to the registers | ||
- | | + | |
- | * w0 through w30 - for 32-bit-wide access (same registers - upper 32 bits are either cleared on load or sign-extended (set to the value of the most significant bit of the loaded value)). | + | * w0 through w30 - for 32-bit-wide access (same registers, specifically accessed 32 bits (or less) at a time - upper 32 bits are either cleared on load or sign-extended (set to the value of the most significant bit of the loaded value)). |
Register ' | Register ' | ||
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* For all other instructions, | * For all other instructions, | ||
- | Usage during [[Syscalls|syscall]]/ | + | Usage during [[Syscalls|syscall]] |
- | * | + | * r0-r7 are used for integer and pointer |
- | * | + | * For syscalls, the syscall number is in r8 |
- | * | + | * r9-r15 are for temporary values |
* r16-r18 are used for intra-procedure-call and platform values (avoid) | * r16-r18 are used for intra-procedure-call and platform values (avoid) | ||
- | * | + | * r19-r28 |
* r29 and r30 are used as the frame register and link register (avoid) | * r29 and r30 are used as the frame register and link register (avoid) | ||
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add r0, | add r0, | ||
adr r0, | adr r0, | ||
- | Register#Program Counter|PC plus an offset) | + | |
- | adrp r0, | + | adrp r0, |
bl label // branch (with link) to label - this is a procedure / subroutine / function call | bl label // branch (with link) to label - this is a procedure / subroutine / function call | ||
br label // branch to label - this is a goto | br label // branch to label - this is a goto | ||
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cmp r0,r1 // compare register r0 with register r1. The comparison sets flags in the processor status register which affect conditional branches. | cmp r0,r1 // compare register r0 with register r1. The comparison sets flags in the processor status register which affect conditional branches. | ||
cmp r0,99 // compare the number 99 with register r0. The comparison sets flags in the processor status register which affect conditional branches. | cmp r0,99 // compare the number 99 with register r0. The comparison sets flags in the processor status register which affect conditional branches. | ||
- | ldr r0,[[r1,0]] // load register r0 from the address pointed to by (r1 + (0 * size)) where size is 8 bytes for 64-bit stores, 4 bytes for 32-bit stores | + | ldr r0, |
- | ldr w0,[[r1,0]] // like above but reads 32 bits only - note the use of w0 instead of r0 for the source register name | + | ldr w0, |
- | ldrb w0,[[r1,0]] // like above but reads 1 byte (8 bits) only - note the use of w0 for the source register name | + | ldrb w0, |
- | ldur r0,[[r1,0]] // load register r0 from the address pointed to by (r1 + 0) - the mnemonic means " | + | ldur r0, |
mov r0,r1 // move data from r1 to r0 | mov r0,r1 // move data from r1 to r0 | ||
mov r0,99 // load r0 with 99 (only certain immediate values are possible) | mov r0,99 // load r0 with 99 (only certain immediate values are possible) | ||
| | ||
- | str r0,[[r1,0]] // store register r0 to address pointed to by (r1 + (0 * //size//)) where //size// is 8 bytes for 64-bit stores | + | str r0, |
- | strb w0,[[r1,0]] // like str but writes one byte only - note the use of w0 for the source register name | + | strb w0, |
- | stur r0,[[r1,0]] // store register r0 to the address pointed to by (r1 + 0) - the mnemonic means "store // | + | stur r0, |
svc 0 // perform a syscall | svc 0 // perform a syscall | ||
msub r0, | msub r0, | ||
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* Character values are indicated by quotation marks. Escapes (such as ' | * Character values are indicated by quotation marks. Escapes (such as ' | ||
* Destinations are given as the first argument (mov r0, r1 moves INTO r0 FROM r1; you can think of this as r0=r1). | * Destinations are given as the first argument (mov r0, r1 moves INTO r0 FROM r1; you can think of this as r0=r1). | ||
- | * For the LDR/STR instructions: | + | * For the LDR/STR instructions: |
* Q = Quadword = 64 bits | * Q = Quadword = 64 bits | ||
* D = Double word = 32 bits | * D = Double word = 32 bits | ||
* W = Word = 16 bits | * W = Word = 16 bits | ||
* B = Byte = 8 bits | * B = Byte = 8 bits | ||
+ | * For any LDR/STR instruction that is loading or storing less than 64 bits, use the narrow (32-bit) version of the register name. For example, '' | ||
===== Resources | ===== Resources | ||
- | * ARM Aarch64 documentation | + | * ARM Aarch64 documentation |
* [[http:// | * [[http:// | ||
* [[https:// | * [[https:// | ||
- | * The //short// guide to the ARMv8 instruction set: [[https:// | + | * Instruction References |
- | * The //long// guide to the ARMv8 instruction set: [[https:// | + | * [[https:// |
- | | + | * [[https:// |
- | * GAS Manual - Using as, The GNU Assembler: | + | |
+ | * [[https:// | ||
spo600/aarch64_register_and_instruction_quick_start.1706886896.txt.gz · Last modified: 2024/04/16 18:10 (external edit)